FIG. 1A is a schematic circuit diagram illustrating a conventional charge pump regulator. FIG. 1B is a schematic timing waveform diagram illustrating associated signal processed by the conventional charge pump regulator of FIG. 1A. The charge pump regulator 100 comprises a charge pump circuit 110 and a feedback detector 120. An output signal Vout is generated by the charge pump regulator 100 and transmitted to a bulk capacitor C and a load 150.
A clock input terminal CK of the charge pump circuit 110 receives an oscillation signal Osc. An output terminal of the charge pump circuit 110 issues the output signal Vout. When the oscillation signal Osc is maintained at a fixed voltage level, the magnitude of the output signal Vout gradually decreases. Whereas, when the oscillation signal Osc is switched between a high level state and a low level state, the magnitude of the output signal Vout gradually increases according to a signal edge (e.g. a rising edge or a falling edge) of the oscillation signal Osc.
Moreover, the feedback detector 120 comprises a voltage divider consisting of two resistors R1 and R2, a comparator 122 and a NAND gate 124. The voltage divider receives the output signal Vout and generates a feedback signal Vfb. A negative input terminal of the comparator 122 receives the feedback signal Vfb. A positive input terminal of the comparator 122 receives a reference voltage Vref. An output terminal of the comparator 122 generates a control signal Vco1. A first input terminal of the NAND gate 124 receives a clock signal CLK. A second input terminal of the NAND gate 124 receives the control signal Vco1. An output terminal of the NAND gate 124 generates the oscillation signal Osc.
In the voltage divider, the relationship between the output signal Vout and the feedback signal Vfb is expressed as: Vfb=(R2×Vout)/(R1+R2). As the magnitude of the output signal Vout increases, the magnitude of the feedback signal Vfb increases. On the other hand, as the magnitude of the output signal Vout decreases, the magnitude of the feedback signal Vfb decreases.
Moreover, if the magnitude of the feedback signal Vfb is higher than the magnitude of the reference voltage Vref, the control signal Vco1 is in the low level state and the oscillation signal Osc is maintained in the high level state. Consequently, the magnitude of the output signal Vout gradually decreases. Whereas, if the magnitude of the feedback signal Vfb is lower than the magnitude of the reference voltage Vref, the control signal Vco1 is in the high level state and the oscillation signal Osc is equal to an inverted clock signal CLK (i.e. Osc= CLK). Consequently, the magnitude of the output signal Vout gradually increases according to the signal edge of the oscillation signal Osc.
When the charge pump regulator 100 reaches the steady state, the output signal Vout is maintained at a level near a target voltage. The target voltage is equal to Vref×(1+R1/R2).
Please refer to FIG. 1B. Before the time point t1, the magnitude of the feedback signal Vfb is lower than the magnitude of the reference voltage Vref. Consequently, the output signal Vout gradually increases. After the time point t1, the feedback signal Vfb reaches a level near the reference voltage Vref. Consequently, the output signal Vout is maintained at a level near the target voltage. The target voltage is equal to Vref×(1+R1/R2).
Since the magnitude of the feedback signal Vfb is sometimes higher than the reference voltage Vref and the magnitude of the feedback signal Vfb is sometimes lower than the reference voltage Vref, the output signal Vout contains ripple. For example, if R1/R2 is equal to 4, the reference voltage Vref is 1.2V and the magnitude of the output signal Vout is 6V, the peak-to-peak ripple voltage of the output signal Vout is about 563 mV.
Please refer to an enlarged fragmentary portion A of FIG. 1B. Theoretically, when the magnitude of the feedback signal Vfb is lower than the reference voltage Vref (at the time point ta), the control signal Vco1 from the comparator 122 should be switched to the high level state. Consequently, the oscillation signal Osc is switched between the high level state and the low level state, and the output signal Vout gradually increases.
However, due to the output delay of the comparator 122, the control signal Vco1 from the comparator 122 is switched to the high level state until the time point tb. That is, during the time period between the time point ta and the time point tb, the oscillation signal Osc is still maintained at the high level state and the magnitude of the output signal Vout continuously decreases by ΔVi. The time period I between the time point ta and the time point tb is referred as a comparator delay period.
At the time point tb, the control signal Vco1 from the comparator 122 is switched to the high level state. However, since the clock signal CLK is still in the low level state, the oscillation signal Osc is still maintained at the high level state and the magnitude of the output signal Vout continuously decreases by ΔVii. Until the time point tc, the clock signal CLK is switched to the high level state. Consequently, the level state of the oscillation signal Osc is switched, and the magnitude of the output signal Vout starts to increase. The time period II between the time point tb and the time point tc is referred as an enable pump delay period.
At the time point td, the control signal Vco1 from the comparator 122 is switched to the low level state. It means that it is not necessary to increase the magnitude of the output signal Vout. Since the clock signal CLK is still in the high level state, the oscillation signal Osc results in a rising edge. Consequently, during the time period between the time point td and the time point te, the magnitude of the output signal Vout continuously increases by ΔViii. The time period III between the time point td and the time point te is referred as a disable pump delay period.
From the above discussions, the comparator delay period I and the enable pump delay period II may result in excess decrease of the output signal Vout, and the disable pump delay period III may result in excess increase of the output signal Vout. That is, due to the excess increase and the excess decrease of the output signal Vout, the peak-to-peak ripple voltage of the output signal Vout is too large.